supertex inc. supertex inc. www.supertex.com HV7355 doc.# dsfp-HV7355 d011314 features ? hvcmos technology for high performance ? high density integrated ultrasound transmitter ? 0 to +150v output voltage ? 1.5a source and sink current (min.) ? 300ma current in cw mode ? up to 18mhz operating frequency ? matched delay times ? built-in gate driver loating voltage regulator ? 2.5 to 3.3v cmos logic interface application ? portable medical ultrasound imaging ? piezoelectric transducer drivers ? ndt ultrasound transmission ? pulse waveform generator general descriptionthe supertex HV7355 is an eight-channel, unipolar, high voltage, high-speed pulse generator. it is designed for medical ultrasound applications. this high voltage and high speed integrated circuit can also be used for other piezoelectric, capacitive or mems sensors in ultrasonic nondestructive detection and sonar ranger applications. the HV7355 consists of a controller logic interface circuit, level translators, mosfet gate drivers and high current p-channel and n-channel mosfets as the output stage for each channel. the output stages of each channel are designed to provide peak output currents over 1.5a for pulsing, when mc = 1, with up to 150v swings. when mc = 0, all the output stages drop the peak current to 500ma for low-voltage cw mode operation to save power. this direct coupling topology of the gate driver not only saves one high voltage capacitor per channel, but also makes the pcb layout easier. typical application circuit eight channel, high speed, unipolar, ultrasound pulser 1.5a 150v lr tx0 lt in0in7 vll vdd vdd vpf vdd vdd vdd vpp gnd mc tx7 vpp vpf vpp vss vss +5.0 to 150v +3.3v cpf vpp vdd lr vpf vdd +5.0v cwd q[7:0] lt lt lt -5.0v d0 sdi q7 sdo sck set le cs en pwr x0 x7 rgndrgnd rgnd +3.3v logic sub q7 q0 avdd vsub data latch shift reg. downloaded from: http:///
2 HV7355 supertex inc. www.supertex.com doc.# dsfp-HV7355 d011314 ordering information part number package options packing HV7355k6-g 56-lead qfn (8x8) 250/tray HV7355k6-g m937 56-lead qfn (8x8) 2000/reel absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. power-up sequence step description 1 v ss 2 v ll with logic signal low 3 v dd 4 v pp 5 en & logic signal go to high power-down sequence step description 1 en & logic signal low 3 v pp 4 v dd 5 v ll 6 v ss pin conigurationpackage marking 1 56 l = lot number yy = year sealed ww = week sealed a = assembler id c = country of origin = ?green? packaging HV7355k6lllllllll yyw w aaa cc c 56-lead qfn 56-lead qfn (top view) package may or may not include the following marks: si or parameter value gnd, rgnd and v sub 0v v ll , positive logic supply -0.5v to +7.0v v dd , positive logic and level translator supply -0.5v to +7.0v v ss , negative level translator and lr supply +0.5v to -7.0v v pp , high voltage positive supply -0.5v to +160v ( v pp -v txx ) voltage -0.5v to +160v (v txx - rgnd) voltage -0.5v to +160v all logic input pin x , nin x and en voltages -0.5v to +7.0v operating temperature -40c to 125c storage temperature -65c to 150c note: powering up/down in any arbitrary sequence will not cause any damage to the device. the powering up/down sequence is only recommended in order to minimize possible inrush current. logic inputs output en q[7:0] in0~7 tx0~7 1 1111,1111 0 gnd 1 1111,1111 1 vpp 1 0 x gnd 0 x x hiz truth table (mc = x) drive mode control table mc i sc (a) r onp r onn 0 0.50 18 13 1 1.6 8.0 3.0 note: v pp = +150v, v dd = +5.0 v, v ll = +3.3v, v ss = -5.0v, v sub = 0v typical thermal resistance package ja 56-lead qfn 21 o c/w -g denotes a lead (pb)-free / rohs compliant package esd sensitive device downloaded from: http:///
3 HV7355 supertex inc. www.supertex.com doc.# dsfp-HV7355 d011314 operating supply voltages and current (eight active channels) (operating conditions, unless otherwise speciied, v ll = +3.3v, v add = v dd = +5.0v, v ss = -5.0v ,v pp = +150v, t a = 25c) sym parameter min typ max units conditions v ll logic voltage reference 2.37 3.30 3.47 v --- v dd internal voltage supply 4.5 5.0 5.5 v --- v pp positive gate driver supply v dd - +150 v --- v ss negative low voltage supply -5.5 -5.0 -4.5 v --- v pf gate driver loating voltage - 5.0 - v --- i ll v ll current en = low - 2.0 10 a --- i ddq v dd current en = low - 50 150 a f = 0mhz i dden v dd current en = high - 1.0 4.0 ma f = 0mhz i dden v dd current mc = high - 160 - ma f = 5.0mhz, continuous no loads i ddencw v dd current mc = low - 12 - ma i ssq v ss current en = low - 5.0 20 a --- i ssen v ss current en = high - 1.0 4.0 ma f = 0mhz i ssen v ss current mc = high - 95 - ma f = 5.0mhz, continuous no loads i ssencw v ss current mc = low - 50 - ma i ppq v pp current en = low - 2.0 10 a --- i ppen v pp current en = high - 200 450 a f = 0mhz i ppen v pp current mc = high - 370 - ma f = 5.0mhz, continuous no loads i ppencw v pp current mc = low - 300 - ma under voltage and over temperature protection sym parameter min typ max units conditions v uvdd v dd threshold 3.4 - 4.4 v (internal only) v uvll v ll threshold - 1.7 - v (internal only) v uvpf v pp - v pf threshold 2.5 - 3.8 v (internal only) logic inputs(operating conditions, unless otherwise speciied, v ll = +3.3v, v add = v dd = +5.0v, v ss = -5.0v ,v pp = +150v, t a = 25c) sym parameter min typ max units conditions v ih input logic high voltage (v ll - 0.4) - v ll v --- v il input logic low voltage 0 - 0.4 v --- i ih input logic high current - - 1.0 a --- i il input logic low current -1.0 - - a --- c in input logic capacitance - - 5.0 pf --- downloaded from: http:///
4 HV7355 supertex inc. www.supertex.com doc.# dsfp-HV7355 d011314 electrical characteristics(operating conditions, unless otherwise speciied, v ll = +3.3v, v add = v dd = +5.0v, v ss = -5.0v ,v pp = +150v, t a = 25c) p-channel mosfet output, tx0~7 sym parameter min typ max units conditions i out output saturation current 1.4 1.6 - a mc = 1 r on channel resistance - 8.0 - 100ma i out output saturation current 0.5 - - a mc = 0 r on channel resistance - 18 - 100ma n-channel mosfet output, tx0~7 sym parameter min typ max units conditions i out output saturation current 1.5 1.7 - a mc = 1 r on channel resistance - 3.0 - i sd = 100ma i out output saturation current 0.5 - - a mc = 0 r on channel resistance - 22 - 100ma ac electrical characteristics( operating conditions, unless otherwise speciied, v ll = +3.3v, v add = v dd = +5.0v, v ss = -5.0v ,v pp = +150v, t a = 25c) sym parameter min typ max units conditions t inrf input data rise/fall max time - - 10 ns --- t r output rise time - 24 - ns 330pf//2.5k load see timing test diagram t f output fall time - 24 - ns f out output frequency range - - 18 mhz 100 resistor load, v pp = +90v t en-on initial enable time - 150 200 s 2f on each cpf pin to 90% of v cpf t en-off output disable time - 2.0 5.0 s at 5.0mhz cw t dr delay time on inputs rise - 5.0 - ns v pp = 25v 1.0 resistor load, 50% to 50%see timing test diagram t df delay time on inputs fall - 5.0 - ns t dm delay on mode change - 50 70 ns t delay delay time matching - 2.0 - ns p to n, channel to channel t j delay jitter on rise or fall - 15 - ps --- serial data interface timing characteristics ( operating conditions, unless otherwise speciied, v ll = +3.3v, v add = v dd = +5.0v, v ss = -5.0v ,v pp = +150v, t a = 25c) sym parameter min typ max units conditions f sck serial clock max. frequency 25 - - mhz all from/to 50% rise or fall edges(see timing diagram) t 1 sdi valid to sck setup time 0 2.0 - ns t 2 sdi valid to sck hold time 4.0 - - ns t 3 sck high time 9.0 - - ns t 4 sck low time 9.0 - - ns t 5 cs pulse width 9.0 - - ns t 6 sck high to cs high 7.0 - - ns t 7 cs low to sck high 7.0 - - ns t 8 sdo delay from sck rise edge - 6.5 - ns sdo with 100pf to gnd t 9 cs high to sck rise edge 7.0 - - ns all from/to 50% rise or fall edges(see timing diagram) t 10 sck high to le low 7.0 - - ns downloaded from: http:///
5 HV7355 supertex inc. www.supertex.com doc.# dsfp-HV7355 d011314 output timing test diagram t drx 50% in x t dfx i out 0a tx x 50% t r t f 90% 10% tx0 lt in0in7 vll vdd vdd vpf vdd vdd vdd vpp gnd mc tx7 vpp vpf vpp vss vss +5.0 to 150v +3.3v cpf vpp vdd lr vpf vdd +5.0v cwd q[7:0] lt lt lt -5.0v d0 sdi q7 sdo sck set le cs en pwr rgnd rgnd rgnd +3.3v logic sub q7 q0 avdd vsub data latch shift reg. r1 serial data interface timing diagram 12378 sck sdi cs sdo le t 1 t 2 t 3 t 4 t 5 t 7 t 8 t 6 t 9 t 10 downloaded from: http:///
6 HV7355 supertex inc. www.supertex.com doc.# dsfp-HV7355 d011314 pin description pin name description 1 in0 input control for channels 0~7 2 in1 3 in2 4 in3 5 in4 6 in5 7 in6 8 in7 9 cs serial interface enable, active low 10 sdi serial shift register data input, msb(d7) irst, lsb(d0) last 11 le latch enable, active low 12 sck serial shift register clock 13 sdo serial shift register data output 14 set set latch data q[7:0] = 1, regardless the shift register inputs or le, active high 15 mc output current mode control pin, see drive mode control table 16 vll logic hi voltage reference input (+3.3v) 17 vss negative power supply(-5.0v) 18 cpf gate driver loating voltage decoupling capacitor to v pp 19 vpp positive high voltage power supply (+150v) 20 vpp 21 vpp 22 vpp 23 vdd positive voltage supply for gate drivers (+5.0v) 24 rgnd output return ground, 0v, rgnd pins carry high current, must connect to load transducer ground 25 rgnd 26 rgnd 27 rgnd downloaded from: http:///
7 HV7355 supertex inc. www.supertex.com doc.# dsfp-HV7355 d011314 pin description (cont.) pin name description 28 tx7 output for channel 0~7 29 tx7 30 tx6 31 tx6 32 tx5 33 tx5 34 tx4 35 tx4 36 tx3 37 tx3 38 tx2 39 tx2 40 tx1 41 tx1 42 tx0 43 tx0 44 rgnd output return ground, 0v, rgnd pins carry high current, must connect to load transducer ground 45 rgnd 46 rgnd 47 rgnd 48 vdd positive voltage supply for gate drivers (+5.0v) 49 vpp positive high voltage power supply (+150v) 50 vpp 51 vpp 52 vpp 53 cpf gate driver loating voltage decoupling capacitor to v pp 54 gnd logic input reference ground, 0v 55 avdd positive internal voltage supply (+5.0v) 56 en chip power enable, active high vsub (thermal pad) substrate bottom is internally connected to the central thermal pad on the bottom of package. it must be connected to gnd (0v) externally downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc . does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2014 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 8 HV7355 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-HV7355 d011314 56-lead qfn package outline (k6) 8.00x8.00mm body, 1.00mm height (max), 0.50mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.80 0.00 0.20 ref 0.18 7.85* 2.75 7.85* 2.75 0.50 bsc 0.30 0.00 0 o nom 0.90 0.02 0.25 8.00 5.70 8.00 5.70 0.40 - - max 1.00 0.05 0.30 8.15* 6.70 ? 8.15* 6.70 ? 0.50 0.15 14 o jedec registration mo-220, variation vlld-2, issue k, june 2006. * this dimension is not speciied in the jedec drawing. ? this dimension differs from the jedec drawing. drawings are not to scale. supertex doc.#: dspd-56qfnk68x8p050, version a031010. notes: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. seating plane top vi ew side view bottom view d e d2 e2 view b vi ew b 1 note 3 note 2 56 1 56 note 1 (index are a d/2 x e/2) note 1 (index are a d/2 x e/2) eb l l1 a a1 a3 downloaded from: http:///
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